SoC Digital Physical Design Engineer
An exciting opportunity for an experienced physical digital design engineer based in Munich, Germany. As a member of the Physical Design team, you will directly own implementation of design partition (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology. You are going to own block level PnR, floor-planning, clock and power distribution. You will get involved STA closure with commercial tools, do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS) and will be developing and validating high performance low power clock network guidelines.
As a Digital Physical Design Engineer, you will:
· Work as part of a team of talented engineers to develop ground-breaking products.
· Take part in the large scale SoC physical design cycle from netlist to tapeout, including full flow of back-end implementation and verification always meeting schedule and design goals.
Required skills for this Digital Design Engineer role:
· Experience with Place & Route ('PnR') tools available today (Synopsys / Cadence)
· Familiar with hierarchical design approach, top-down design, and timing and physical convergence
· Demonstrate in-depth understanding of STA, extensive know-how in clock/power distribution and analysis, as well as RC extraction and correlation
· Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration
· Hold a MSEE or equivalent strong experience.
· Excellent communication skills in English
If you are interested in this SoC Digital Physical Design Engineer role, please send a CV to firstname.lastname@example.org
Keywords: Physical Design, Place & Route ('PnR'), Synopsys / Cadence, top-down design, timing and physical convergence, STA, clock and power, floor-planning, netlist, GDS, DRC/LVS, physical implementation, digital backend, digital layout
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