Physical Design Engineer (Synopsys / Cadence / Place and Route (PnR) / Static Timing / EM / IR-Drop / Xtalk / DRC / LVS)
We are recruiting for multiple Physical Design Engineers to join my client in the Munich area on a permeant basis.
My client is a globally known technically company (household name) and as a Physical Design Engineer you should have prior experience with one of the Place & Route ('PnR') tools available today (Synopsys / Cadence), and having understanding of their capabilities and underlying algorithms and you should be familiar with hierarchical design approach, top-down design, and timing and physical convergence.
As a member of the Physical Design team in this highly visible role, you will directly own
implementation of design partitions for a highly complex SoC utilizing state of the art process technology
· You are going to own block level PnR, floor-planning, clock and power distribution
· You will get involved with static timing closure with commercial tools
· You will do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC
· / LVS)
· You will be developing and validating high performance low power clock network guidelines
· With great focus you will resolve design and flow issues related to physical design, and
· identify potential solutions whilst driving execution
· You know what documentation should look like, and will help with guidelines and specs
· You should hold a MSEE or equivalent strong experience
Key words: SoC / Digital Physical Design / Synopsys / Cadence / Place and Route (PnR) / Static Timing / EM / IR-Drop / Xtalk / DRC / LVS
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