Digital Verification Engineer - UVM/System Verilog/IP
Are you looking for your next exciting challenge? Our globally-renowned semiconductor client is looking for experienced digital verification engineersto join their site in Lund Hamburg.
You will be working with UVM and System Verilog technologies on formal verification/system level verification for IP/SoC.
Key skills required for this Digital Verification Engineer role include:
If you are interested in this Digital Verification Engeerin position, apply directly to this advert or email me at firstname.lastname@example.org
Keywords: Digital Verification, UVM, ASIC, FPGA, RTL, SOC, Verilog, System Verilog, OVM, EDA, Formal Verification, Block Level Verification, Soc Level Verification, Semiconductors, IP, IC, Integrated Circuits, VHDL, TCL, Perl, Python
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