Senior Digital Verification Engineer / UVM / SYSTEM VERILOG

  • by European Recruitment
  • Location Hamburg, Germany
  • Salary £70,000 - £90,000 / year
  • 140 days ago
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Job Description:

Senior Digital Verification Engineer / UVM / SYSTEM VERILOG

I currently have an interesting opportunity for a Senior Digital Verification Engineer. You will be working with a leading technology company on a permanent basis, carrying out a range of different projects based in either Hamburg, Graz or Eindhoven.

Key Experience and requirements include;

  •  A degree in Engineering with 5+ years of experience
  • Deep understanding of directed and constrained random verification methodology
  • Solid understanding of the architecture and functionality of SOCs
  • Understanding of software development for embedded CPUs, and experience in developing and debugging Software.

Responsibilities;

  • Responsible for the complete functional verification at block level and SOC level
  • Develop, debug, and modify the test environment for different platforms 
  • Define the verification strategy for specific IP modules as a function of system architecture, the expected use cases, technology, and schedule constraints
  • Define and code test cases in an appropriate language and debug these test cases on the design models and on silicon.

If you are interested please get in touch at mrd@eu-recruit.com

  • Job Type Permanent, Full Time
  • Work Authorisation No
  • Industry Sector Electronics
  • Years Experience 5+ years
  • Career Level Experienced (Non-Manager)
  • Educational level Master's Degree