Digital Verification Engineer - VHDL / Verilog / UVM

  • by European Recruitment
  • Location Austria
  • Salary negotiable
  • 180 days ago
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Job Description:

Digital Verification Engineer - VHDL / Verilog / UVM 


We are recruiting for a Digital Verification Engineer with extensive knowledge of VHDL, Verilog and UVM to join our client at their HQ in Austria. 


As a Digital Verification Engineer you will be responsible for creating and maintaining verification plans, define verification metrics, and execute tests on RTL.


Digital Verification required skills:

  • Degree in Electrical Engineering or similar 
  • 5+ years experience in pre-silicon verification 
  • Good knowledge of VHDL, Verilog, Specman 
  • Project experience using UVM, OVM, SVA
  • Good knowledge of Unix programming languages

Key words:

Verification / Digital /  VHDL / Verilog / UVM 


  • Job Type Permanent, Full Time
  • Additional Salary Info Competitive salary for the Austrian market
  • Work Authorisation No
  • Industry Sector Engineering, Utilities
  • Years Experience 5+ years