SENIOR DIGITAL VERIFICATION ENGINEER (UVM, SYSTEM VERILOG, ASSERTION)

  • by European Recruitment
  • Location Munich, Munich, Germany
  • Salary €68,000 - €100,000 / year
  • 47 days ago

European Recruitment

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Job Description:

SENIOR DIGITAL VERIFICATION ENGINEER (UVM, SYSTEM VERILOG, ASSERTION)

 

We are now hiring for a Verification Design Engineer - Verification of digital blocks and top level in digital domain of power management circuits for battery operated portable devices. The successful candidate will to join their expanding team in Munich on a permanent basis.

 

The key skills required for the Verification Design Engineer role are:

  • Several years of experience in digital verification 
  • Familiar with advanced verification techniques (e.g UVM, System Verilog, Assertions)
  • Experience with constrained random verification of digital logic

 

In terms of education a master or above is ideal, however we will consider a bachelors.

 

Senior Digital Verification Engineer job

 

Key Words: Verification Design Engineer / UVM, System Verilog, Assertion / Digital Logic / Random Verification / RTL Coding / Germany / Munich / Permanent / Design / Digital / Senior / Verification.

  • Job Type Permanent, Full Time
  • Additional Salary Info RELOACTION IF NEEDED, BONUSES + R
  • Work Authorisation No
  • Industry Sector Electronics